Semiconductor memory apparatus and method for correcting duty thereof

ABSTRACT

A semiconductor memory apparatus may comprise a duty cycle correction circuit configured to perform a duty correction operation with respect to an input clock signal when a delay locked signal is activated, and perform the duty correction operation with respect to the input signal when a precharge signal is activated, to generate a corrected clock signal.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) toKorean Application No. 10-2011-0009804, filed on Jan. 31, 2011, in theKorean Intellectual Property Office, which is incorporated herein byreference in its entirety as if set forth in full.

BACKGROUND

1. Technical Field

Various embodiments of the present invention relate to a semiconductormemory apparatuses and related methods. In particular, certainembodiments relate to a semiconductor memory apparatus including a dutycycle correction circuit and related method for correcting the dutycycle.

2. Related Art

A duty cycle correction circuit is extensively used to correct a duty ofa clock generated in a delay locked loop of a semiconductor memoryapparatus.

The delay locked loop receives an external clock signal, performs adelay locked operation with respect to the external clock signal togenerate an internal clock signal, and generates a delay locked signalwhen a delay value for the internal clock signal is locked.

When the delay locked signal is activated, the duty cycle correctioncircuit receives the internal clock signal as an input clock signal, andperforms a duty correction operation with respect to the input clocksignal to generate a corrected clock signal.

Here, on the basis of a single cycle of a clock signal with apredetermined frequency, duty refers to a ratio of a time during which aclock signal is in a logic low state to a time during which the clocksignal is in a logic high state. When the time during which the clocksignal is in the logic low state is substantially same as the timeduring which the clock signal is in the logic high state, the duty is50%.

In a conventional semiconductor memory apparatus, a delay locked loopand a duty cycle correction circuit can perform a delay locked operationand a duty correction operation with respect to a clock signal only whenthe semiconductor memory apparatus is initialized, in order to reducecurrent consumption in the delay locked operation and the dutycorrection operation during a read operation and a write operation.

After initialization, the conventional semiconductor memory apparatusmay substantially maintain preset delay value and duty value withoutperforming the delay locked operation and the duty correction operation.Thus, in the conventional semiconductor memory apparatus, the dutycorrection operation is started when the delay value of the delay lockedloop is locked and repeated multiple times until the duty is correctedto be above a predetermined level. When the duty is corrected to beabove the predetermined level, the set duty value is maintained andvarious duty correction operations are stopped.

However, if the duty correction operations are finished, it may not bepossible to correct a distortion of a duty of a clock signal which isinput after the duty correction operations are finished.

FIG. 1 is a block diagram of a related-art duty cycle correctioncircuit.

Referring to FIG. 1, the duty cycle correction circuit includes acorrection execution unit 10, a duty detection unit 20, a dutydetermination unit 30, and a correction code generation unit 40.

The correction execution unit 10 corrects a duty of an input clocksignal CLK_d based on a multi-bit correction code DCC_CODE<0:n> togenerate a corrected clock signal CLK.

The duty detection unit 20 checks the duty of the corrected clock signalCLK to generate a detection voltage det, which is an analog voltage.

The duty determination unit 30 generates a determination signal conbased on the detection voltage det.

For example, the duty determination unit 30 activates the determinationsignal con when the detection voltage det is larger than a predeterminedvoltage, and deactivates the determination signal con when the detectionvoltage det is smaller than the predetermined voltage. The fact that thedetection voltage det is larger than the predetermined voltagerepresents that the duty of the clock signal CLK has been distorted soas not to reach a predetermined level (for example, 60%). Meanwhile, thefact that the detection voltage det is smaller than the predeterminedvoltage represents that the duty of the clock signal CLK exists withinthe predetermined level.

The correction code generation unit 40 generates the multi-bitcorrection code DCC_CODE<0:n> in response to a delay locked signal Lockstate, the detection voltage det, and the determination signal con.

The delay locked signal Lock state is activated after the delay lockedloop locks a delay value for the clock signal CLK.

When the delay locked signal Lock state and the determination signal conare activated, the correction code generation unit 40 starts anoperation of generating the multi-bit correction code DCC_CODE<0:n>based on the detection voltage det, is which is an analog voltage. Whenthe determination signal con is deactivated, the correction codegeneration unit 40 completes the operation of generating the multi-bitcorrection code DCC_CODE<0:n> based on the detection voltage.

As described above, the duty cycle correction circuit according to theconventional art is formed in a closed loop as illustrated in FIG. 1,thereby continuously correcting the duty of the clock signal CLK.

SUMMARY

In the following description, certain aspects and embodiments willbecome evident. It should be understood that these aspects andembodiments are merely exemplary, and the invention, in its broadestsense, could be practiced without having one or more features of theseaspects and embodiments.

In one exemplary aspect of the present invention, a semiconductor memoryapparatus may comprise a duty cycle correction circuit configured toperform a duty correction operation with respect to an input clocksignal when a delay locked signal is activated, and perform the dutycorrection operation with respect to the input signal when a prechargesignal is activated, to generate a corrected clock signal.

In another exemplary aspect of the present invention, a semiconductormemory apparatus may comprise: a delay locked circuit configured toreceive an external clock signal to generate an input clock signal byperforming a delay locked operation with respect to the external clocksignal, and generate a delay locked signal when the delay lockedoperation is completed; and a duty correction circuit configured toperform a duty correction operation with respect to the input clocksignal and generate a corrected clock signal. The duty correctioncircuit may be configured to perform the duty correction operation whenthe delay locked signal is activated, and duty correction circuit isfurther configured to perform the duty correction operation when theprecharge signal is activated.

In yet another exemplary aspect of the present invention, a method forcorrecting a duty of a semiconductor memory apparatus may comprise:receiving an external clock signal; performing a delay locked operationwith respect to the external clock signal to generate an input clocksignal and activating a delay locked signal; performing a dutycorrection operation with respect to the input clock signal in responseto the delay locked signal and generating a corrected clock signal;activating a precharge signal; and performing the duty correctionoperation with respect to the input clock signal in response to theprecharge signal and generating the corrected clock signal.

In still another exemplary aspect of the present invention, asemiconductor memory apparatus includes a duty cycle correction circuitconfigured to perform a duty correction operation with respect to aninput clock signal in response to a precharge signal to generate acorrected clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate various embodiments consistentwith the invention and, together with the description, serve to explainthe principles of the invention.

FIG. 1 is a block diagram of a related-art duty cycle correctioncircuit;

FIG. 2 is a schematic block diagram of a semiconductor memory apparatusincluding a duty cycle correction circuit according to an exemplaryembodiment;

FIG. 3 is a detailed block diagram of the duty correction circuitillustrated in FIG. 2;

FIG. 4 is a circuit diagram of the activation signal generation blockillustrated in FIG. 3 according to an exemplary embodiment;

FIG. 5 is a waveform diagram illustrating the operation of the dutycorrection circuit illustrated in FIGS. 2 to 4;

FIG. 6 is a schematic block diagram of a semiconductor memory apparatusincluding a duty cycle correction circuit according to an exemplaryembodiment; and

FIG. 7 is a circuit diagram of the activation signal generation blockillustrated in FIG. 6 according to an exemplary embodiment.

DETAILED DESCRIPTION

Reference will now be made in detail to the exemplary embodimentsconsistent with the present disclosure, examples of which areillustrated in the accompanying drawings. Wherever possible, the samereference characters will be used throughout the drawings to refer tothe same or like parts.

A duty cycle correction circuit of a semiconductor memory apparatusaccording to the present invention performs a duty correction operationin response to a delay locked signal Lock state, and additionallyperforms the duty correction operation for a predetermined time when thesemiconductor memory apparatus performs a precharge operation.

A semiconductor memory apparatus according to the present invention cancorrect the duty of a corrected clock signal CLK throughout a normaloperation as well as an initialization operation since the prechargeoperation is frequently performed in order to preserve stored data whenthe semiconductor memory apparatus is not performing a read or a writeoperation.

A semiconductor memory apparatus according to the present invention mayadvantages of high speed and low voltage operations, since a duty of aclock signal is an important factor for stably performing high speed andlow voltage operations in a semiconductor memory apparatus,

FIG. 2 is a schematic block diagram of a semiconductor memory apparatus1 including a duty cycle correction circuit according to an exemplaryembodiment.

The semiconductor memory apparatus 1 may comprise a delay locked circuit1000 and a duty correction circuit 2000.

The delay locked circuit 1000 is configured to receive an external clocksignal CLK_EXT, perform a delay locked operation with respect to theexternal clock signal CLK_EXT, and generate an input clock signal CLK_d.

If the delay locked operation is completed, the delay locked circuit1000 generates a delay locked signal Lock state.

The delay locked circuit 1000 may include a general delay locked loop.

The duty correction circuit 2000 is a duty cycle correction circuit andis configured to generate a corrected clock signal CLK by performing aduty correction operation with respect to the input clock signal CLK_dwhen the delay locked signal Lock state is activated. The dutycorrection circuit 2000 generates the corrected clock signal CLK byadditionally performing the duty correction operation with respect tothe input clock signal CLK_d when a precharge signal IDLE is activated.

Thus, a duty correction operation for the input clock signal CLK_d forgenerating the corrected clock signal CLK is performed when either thedelay locked signal Lock state or the precharge signal IDLE isactivated.

The corrected clock signal CLK may be used as an internal clock signalof the semiconductor memory apparatus.

The precharge signal IDLE is activated when a precharge command isgenerated in the semiconductor memory apparatus 1.

The semiconductor memory apparatus 1 configured as mentioned aboveperforms the duty correction operation in response to the delay lockedsignal Lock state generated during an initialization operation, therebyinitially correcting the duty value of the corrected clock signal CLK.Furthermore, the semiconductor memory apparatus 1 additionally performsthe duty correction operation in response to the precharge signal IDLEgenerated in each precharge operation during the normal operation,thereby additionally correcting the duty value of the corrected clocksignal CLK.

In a typical semiconductor memory apparatus, duty distortion after theinitialization operation may not be corrected since a duty value set inan initialization operation is continuously maintained. However, in thesemiconductor memory apparatus 1 according to an exemplary embodiment,the duty correction operation is performed even in a normal operation,so that it is possible to correct duty distortion after theinitialization operation.

In the semiconductor memory apparatus 1 according to the exemplaryembodiment, the duty correction operation performed in each prechargeoperation may be performed in a shorter time than the duty correctionoperation performed in the initialization operation, in order to reducepower consumption during duty correction. This is because the dutydistortion of the external clock signal CLK_EXT which is input in thenormal operation is sufficiently smaller than the duty distortioncorrected in the initialization operation.

FIG. 3 is a detailed block diagram of the duty correction circuit 2000illustrated in FIG. 2.

Referring to FIG. 3, the duty correction circuit 2000 may comprise acorrection block 100 and an activation signal generation block 200.

The correction block 100 is configured to generate a detection voltagedet based on the duty of the input clock signal CLK_d, correct the dutyof the input clock signal CLK_d in response to an activation signal act,and generate the corrected clock signal CLK.

The correction block 100 may comprise a correction execution unit 10, aduty detection unit 20, and a correction code generation unit 41.

The correction execution unit 10 is configured to correct the duty ofthe input clock signal CLK_d based on the multi-bit correction codeDCC_CODE<0:n> and generate the corrected clock signal CLK. Furthermore,the correction execution unit 10 is configured to provide the dutydetection unit 20 with the corrected clock signal CLK.

The correction execution unit 10 may have a substantially sameconfiguration as that of the general correction execution unit 10illustrated in FIG. 1.

The duty detection unit 20 is configured to check the duty of thecorrected clock signal CLK and generate a detection voltage det which isan analog voltage.

For example, the duty detection unit 20 may be configured to check theduty of the corrected clock signal CLK and generate a low detectionvoltage det as the duty approaches 50%.

The duty detection unit 20 may have a substantially same configurationas that of the general duty detection unit 20 illustrated in FIG. 1.

The correction code generation unit 41 is configured to generate themulti-bit correction code DCC_CODE<0:n> based on the detection voltagedet when the activation signal act is activated.

The correction code generation unit 41 may comprise general voltagedivider, comparator and counter circuit, which are activated based onthe activation signal act.

The activation signal generation block 200 is configured to generate theactivation signal act based on the delay locked signal Lock state, theprecharge signal IDLE, and the detection voltage det.

For example, the activation signal generation block 200 activates theactivation signal act based on the detection voltage det when the delaylocked signal Lock state is activated, and also activates the activationsignal act when the precharge signal IDLE is activated.

The activation signal generation block 200 configured as mentioned aboveperforms the duty correction operation with respect to the input clocksignal CLK_d until the duty of the corrected clock signal CLK reaches apredetermined level and the detection voltage det falls below apredetermined level when the delay locked signal Lock state isactivated.

Furthermore, the activation signal generation block 200 may additionallyperform the duty correction operation for a predetermined time when theprecharge signal IDLE is activated.

FIG. 4 is a circuit diagram of the activation signal generation block200 illustrated in FIG. 3 according to an exemplary embodiment.

The activation signal generation block 200 may comprise a dutydetermination unit 30 and a signal combination unit 210.

The duty determination unit 30 is configured to generate a determinationsignal con based on the detection voltage det.

For example, the duty determination unit 30 may be configured toactivate the determination signal con when the detection voltage det islarger than a predetermined voltage, and deactivate the determinationsignal con when the detection voltage det is smaller than thepredetermined voltage.

The duty determination unit 30 may have a substantially sameconfiguration as that of the duty determination unit 30 illustrated inFIG. 1. For example, the duty determination unit 30 may comprise ageneral comparator.

The signal combination unit 210 is configured to generate the activationsignal act in response to the precharge signal IDLE, the delay lockedsignal Lock state, and the determination signal con.

The signal combination unit 210 may be configured to activate theactivation signal act when both the delay locked signal Lock state andthe determination signal con are activated, and additionally activatethe activation signal act when the precharge signal IDLE is activated.

The signal combination unit 210 may comprise a first activation section211, a second activation section 212, and an adding section 213.

The first activation section 211 is configured to generate a firstactivation period signal a1 which is activated during the period inwhich the delay locked signal Lock state and the determination signalcon are activated.

The first activation section 211 may comprise an AND gate 4001.

The AND gate 4001 is configured to perform an AND operation on the delaylocked signal Lock state and the determination signal con and output thefirst activation period signal a1.

The second activation section 212 is configured to generate a secondactivation period signal a2 with a predetermined pulse width when theprecharge signal IDLE is activated.

The precharge signal IDLE is activated in response to a prechargecommand and the pulse width thereof may be insufficient to be used forthe duty correction operation of the duty correction circuit 2000.Therefore, the second activation section 212 illustrated in FIG. 4 isconfigured to convert the precharge signal IDLE to a signal with a pulsewidth sufficient for the duty correction operation.

The second activation section 212 may comprise a delay inversion part212-1 and an AND gate 4002.

The delay inversion part 212-1 is configured to delay and invert theprecharge signal IDLE for a predetermined time and output an invertedsignal.

The AND gate 4002 is configured to perform an AND operation on theprecharge signal IDLE and the output signal of the delay inversion part212-1 and output the second activation period signal a2.

The second activation section 212 configured as mentioned above maygenerate the second activation period signal a2 with a pulse widthcorresponding to the delay time of the delay inversion part 212-1.

The adding section 213 is configured to add the first activation periodsignal a1 to the second activation period signal a2 and generate theactivation signal act.

The signal combination unit 210 configured as illustrated in FIG. 4 maygenerate the activation signal act having a period in which the delaylocked signal Lock state and the determination signal con have beenactivated, and a period activated for a predetermined time from the timepoint at which the precharge signal IDLE has been activated.

The delay inversion part 212-1 may comprise a general delay circuit andan inverter.

Furthermore, the delay inversion part 212-1 may comprise a delayflip-flop that receives the corrected clock signal CLK or the externalclock signal CLK_EXT. When the delay inversion part 212-1 includes thedelay flip-flop, the delay time of the delay inversion part 212-1 maysynchronize with the corrected clock signal CLK. Since the semiconductormemory apparatus 1 operates in synchronization with the corrected clocksignal CLK, the synchronization with the corrected clock signal CLKwithout the delay time of the delay inversion part 212-1 may beadvantageous in dealing with a change in the operation characteristicsof the semiconductor memory apparatus 1.

FIG. 5 is a waveform diagram illustrating the operation of the dutycorrection circuit 2000 illustrated in FIGS. 2 to 4.

Referring to FIG. 5, the delay locked operation of the delay lockedcircuit 1000 is completed and the delay locked signal Lock state isactivated to a high level.

The duty detection unit 20 checks the duty of the corrected clock signalCLK and outputs the detection voltage det.

Furthermore, the duty determination unit 30 checks that the detectionvoltage det is equal to or more than a predetermined level and activatesthe determination signal con to a high level as illustrated in FIG. 5.This represents that the duty of the corrected clock signal CLK has notreached a predetermined level. In general, the ideal duty of thecorrected clock signal CLK is 50%.

The precharge signal IDLE maintains a high level state according to theinitialization operation of the semiconductor memory apparatus 1.

Thus, as illustrated in FIG. 5, the signal combination unit 210activates the activation signal act to a high level in response to theactivation to high levels of the delay locked signal Lock state and thedetermination signal con. That is, the activation signal act isactivated for during the period in which the delay locked signal Lockstate and the determination signal con are at high levels.

The correction code generation unit 41 generates the multi-bitcorrection code DCC_CODE<0:n> based on the detection voltage det inresponse to the activation signal act.

As illustrated in FIG. 5, the multi-bit correction code DCC_CODE<0:n> isgenerated by the correction code generation unit 41 multiple timesduring the period in which the activation signal act is activated.

As the multi-bit correction code DCC_CODE<0:n> is generated multipletimes, the correction execution unit 10 performs the duty correctionoperation with respect to the corrected clock signal CLK multiple times.As the degree of the correction for the duty of the corrected clocksignal CLK approaches the predetermined level (for example, 50%), thelevel of the detection voltage det generated by the duty detection unit20 falls.

Referring to FIG. 5, as the detection voltage det falls below thepredetermined level, the duty determination unit 30 deactivates thedetermination signal con to a low level.

Furthermore, as the determination signal con is deactivated to the lowlevel, the activation signal act is deactivated to a low level by thesignal combination unit 210.

As the activation signal act is deactivated, the correction codegeneration unit 41 stops generating the multi-bit correction codeDCC_CODE<0:n>.

Then, the semiconductor memory apparatus 1 completes the initializationoperation and starts the normal operation.

In the normal operation of the semiconductor memory apparatus 1, theprecharge signal IDLE is activated to a high level in response to theprecharge command.

FIG. 5 illustrates that the activation signal act is activated by thesignal combination unit 210 for a predetermined time as the prechargesignal IDLE is activated to the high level.

Thus, the correction code generation unit 41 generates the multi-bitcorrection code DCC_CODE<0:n> based on the detection voltage det inresponse to the activation signal act.

As described above, the duty correction operation performed in responseto the precharge signal IDLE may be performed for a shorter time thanthe duty correction operation performed in response to the delay lockedsignal Lock state.

As illustrated in FIG. 5, during the activation period of the activationsignal act activated in response to the precharge signal IDLE, themulti-bit correction code DCC_CODE<0:n> is generated once without beinglimited by the correction code generation unit 41.

FIG. 6 is a schematic block diagram of a semiconductor memory apparatus2 including a duty cycle correction circuit according to anotherexemplary embodiment.

The semiconductor memory apparatus 2 illustrated in FIGS. 2 to 5 isconfigured to perform the duty correction operation after the delaylocked operation of the delay locked circuit 1000 and in the prechargeoperation.

However, the semiconductor memory apparatus 2 illustrated in FIG. 6 isconfigured to not perform the duty correction operation after the delaylocked operation of the delay locked circuit 1000, and to perform theduty correction operation in the precharge operation.

The semiconductor memory apparatus 2 does not perform the dutycorrection operation after the delay locked operation of the delaylocked circuit 1000, so that it is possible to reduce the time necessaryfor the initialization operation of the semiconductor memory apparatus2.

Consequently, the semiconductor memory apparatus 2 illustrated in FIG. 6is sufficient to be used for a semiconductor memory apparatus with nodelay locked loop.

The duty cycle correction circuit of the semiconductor memory apparatus2 illustrated in FIG. 6 may comprise a correction block 300 and anactivation signal generation block 400.

The correction block 300 is configured to perform a duty correctionoperation with respect to an input clock signal CLK_d in response to anactivation signal act, and generate a corrected clock signal CLK.

The activation signal generation block 400 is configured to generate theactivation signal act in response to a precharge signal IDLE.

The correction block 300 may comprise a correction execution unit 10, aduty detection unit 20, and a correction code generation unit 41.

The correction execution unit 10 is configured to perform the dutycorrection operation with respect to the input clock signal CLK_d basedon the multi-bit correction code DCC_CODE<0:n> and generate thecorrected clock signal CLK. Furthermore, the correction execution unit10 is configured to provide the duty detection unit 20 with thecorrected clock signal CLK.

The correction execution unit 10 may have a substantially sameconfiguration as that of the general correction execution unit 10illustrated in FIGS. 1 and 3.

The duty detection unit 20 is configured to check the duty of thecorrected clock signal CLK and generate a detection voltage det which isan analog voltage.

For example, the duty detection unit 20 may be configured to check theduty of the corrected clock signal CLK and generate a low detectionvoltage det as the duty approaches 50%.

The duty detection unit 20 may have a substantially same configurationas that of the general duty detection unit 20 illustrated in FIGS. 1 and3.

The correction code generation unit 41 is configured to generate themulti-bit correction code DCC_CODE<0:n> based on the detection voltagedet when the activation signal act is activated.

The correction code generation unit 41 may include general voltagedivider and counter circuit, which are activated based on the activationsignal act.

In the duty cycle correction circuit configured as illustrated in FIG.6, the activation signal generation block 400 is configured to activateand output the activation signal act whenever the precharge signal IDLEis activated.

Thus, the correction code generation unit 41 generates the multi-bitcorrection code DCC_CODE<0:n> in response to the activation signal actwhenever the precharge signal IDLE is activated.

Furthermore, the correction execution unit 10 performs the dutycorrection operation with respect to the input clock signal CLK_d inresponse to the multi-bit correction code DCC_CODE<0:n> whenever theprecharge signal IDLE is activated.

FIG. 7 is a circuit diagram of the activation signal generation block400 illustrated in FIG. 6 according to another exemplary embodiment.

The activation signal generation block 400 may have a configurationsimilar to that of the second activation section 212 illustrated in FIG.4.

The activation signal generation block 400 may comprise a delayinversion part 212-1 and an AND gate 7001.

The delay inversion part 212-1 is configured to delay and invert theprecharge signal IDLE for a predetermined time and output an invertedsignal. The delay inversion part 212-1 may have a substantially sameconfiguration as that of the delay inversion part 212-1 illustrated inFIG. 4.

The AND gate 7001 is configured to perform an AND operation on theprecharge signal IDLE and the output signal of the delay inversion part212-1 and output the activation signal act.

The activation signal generation block 400 configured as mentioned abovemay generate the activation signal act with a pulse width correspondingto the delay time of the delay inversion part 212-1.

While certain embodiments have been described above, it will beunderstood to those skilled in the art that the embodiments describedare by way of example only. Accordingly, the semiconductor memoryapparatus and the method for correcting the duty thereof describedherein should not be limited based on the described embodiments. Rather,the semiconductor memory apparatus and the method for correcting theduty thereof described herein should only be limited in light of theclaims that follow when taken in conjunction with the above descriptionand accompanying drawings.

1. A semiconductor memory apparatus comprising: a duty cycle correctioncircuit configured to perform a duty correction operation with respectto an input clock signal when a delay locked signal is activated, andperform the duty correction operation with respect to the input clocksignal when a precharge signal is activated, to generate a correctedclock signal.
 2. The semiconductor memory apparatus according to claim1, wherein the duty cycle correction circuit comprises: a correctionblock configured to perform the duty correction operation with respectto the input clock signal based on an activation signal to generate thecorrected clock signal, and generate a detection voltage based on a dutyof the corrected clock signal; and an activation signal generation blockconfigured to generate the activation signal based on the delay lockedsignal, the precharge signal and the detection voltage.
 3. Thesemiconductor memory apparatus according to claim 2, wherein thecorrection block comprises: a correction execution unit configured toperform the duty correction operation with respect to the input clocksignal based on a correction code and generate the corrected clocksignal; a duty detection unit configured to generate the detectionvoltage based on the duty of the corrected clock signal; and acorrection code generation unit configured to generate the correctioncode based on the detection voltage in response to the activationsignal.
 4. The semiconductor memory apparatus according to claim 2,wherein the activation signal generation block is configured to activatethe activation signal based on the detection voltage when the delaylocked signal is activated, and additionally activate the activationsignal when the precharge signal is activated.
 5. The semiconductormemory apparatus according to claim 4, wherein the activation signalgeneration block comprises: a duty determination unit configured togenerate a determination signal based on the detection voltage; and asignal combination unit configured to generate the activation signal inresponse to the precharge signal, the delay locked signal, and thedetermination signal.
 6. The semiconductor memory apparatus according toclaim 5, wherein the signal combination unit is configured to activateand output the activation signal when at least one of the delay lockedsignal, the precharge signal and the determination signal is activated.7. The semiconductor memory apparatus according to claim 6, wherein thesignal combination unit comprises: a first activation section configuredto generate a first activation period signal which is activated during aperiod in which both a delay locked signal and the determination signalare activated; a second activation section configured to activate asecond activation period signal with a predetermined pulse width whenthe precharge signal is activated; and an adding section configured toadd the first activation period signal to the second activation periodsignal and generate the activation signal.
 8. The semiconductor memoryapparatus according to claim 7, wherein the second activation section isconfigured to allow the second activation period signal to have apredetermined pulse width is using a pulse width of the clock signal. 9.The semiconductor memory apparatus according to claim 7, wherein thepredetermined pulse width corresponds to a time necessary for thecorrection code generation unit to generate the correction code once.10. The semiconductor memory apparatus according to claim 1, wherein atime necessary to perform the duty correction operation when theprecharge signal is activated is shorter than a time necessary toperform the duty correction operation when the delay locked signal isactivated.
 11. A semiconductor memory apparatus comprising: a delaylocked circuit configured to receive an external clock signal togenerate an input clock signal by performing a delay locked operationwith respect to the external clock signal, and generate a delay lockedsignal when the delay locked operation is completed; and a dutycorrection circuit configured to perform a duty correction operationwith respect to the input clock signal and generate a corrected clocksignal, wherein the duty correction circuit is configured to perform theduty correction operation when the delay locked signal is activated, andthe duty correction circuit is further configured to perform the dutycorrection operation when the precharge signal is activated.
 12. Thesemiconductor memory apparatus according to claim 11, wherein the dutycorrection circuit comprises: a correction block configured to performthe duty correction operation with respect to the input clock signalbased on an activation signal to generate the corrected clock signal,and generate a detection voltage based on a duty of the corrected clocksignal; and an activation signal generation block configured to generatethe activation signal based on the delay locked signal, the prechargesignal, and the detection voltage.
 13. The semiconductor memoryapparatus according to claim 12, wherein the correction block comprises:a correction execution unit configured to correct a duty of the clocksignal based on a correction code; a duty detection unit configured togenerate a detection voltage based on the duty of the clock signal; anda correction code generation unit configured to generate the correctioncode based on the detection voltage in response to the activationsignal.
 14. The semiconductor memory apparatus according to claim 12,wherein the activation signal generation block is configured to activatethe activation signal based on the detection voltage when the delaylocked signal is activated, and additionally activate the activationsignal when the precharge signal is activated.
 15. The semiconductormemory apparatus according to claim 14, wherein the activation signalgeneration block comprises: a duty determination unit configured togenerate a determination signal based on the detection voltage; and asignal combination unit configured to generate the activation signal inresponse to the precharge signal, the delay locked signal, and thedetermination signal.
 16. The semiconductor memory apparatus accordingto claim 15, wherein the signal combination unit is configured toactivate and output the activation signal when at least one of the delaylocked signal, the determination signal, or the precharge signal isactivated.
 17. The semiconductor memory apparatus according to claim 16,wherein the signal combination unit comprises: a first activationsection configured to generate a first activation period signal which isactivated during a period in which the delay locked signal and thedetermination signal are activated; a second activation sectionconfigured to activate a second activation period signal with apredetermined pulse width when the precharge signal is activated; and anadding section configured to add the first activation period signal tothe second activation period signal and generate the activation signal.18. The semiconductor memory apparatus according to claim 16, whereinthe second activation section is configured to allow the secondactivation period signal to have a predetermined pulse width using apulse width of the clock signal.
 19. The semiconductor memory apparatusaccording to claim 17, wherein the predetermined pulse width correspondsto a time necessary for the correction code generation unit to generatethe correction code once.
 20. The semiconductor memory apparatusaccording to claim 11, wherein a time necessary to perform the dutycorrection operation when the precharge signal is activated is shorterthan a time necessary to perform the duty correction operation when thedelay locked signal is activated.
 21. A method for correcting a duty ofa semiconductor memory apparatus, comprising: receiving an externalclock signal; performing a delay locked operation with respect to theexternal clock signal to generate an input clock signal and activating adelay locked signal; performing a duty correction operation with respectto the input clock signal in response to the delay locked signal andgenerating a corrected clock signal; activating a precharge signal; andperforming the duty correction operation with respect to the input clocksignal in response to the precharge signal and generating the correctedclock signal.
 22. The method according to claim 21, wherein performingthe duty correction operation with respect to the input clock signal inresponse to the delay locked signal is performed n times until a duty ofthe input clock signal is corrected to a predetermined level, andperforming the duty correction operation with respect to the input clocksignal in response to the precharge signal is performed m times, whereinthe m is an integer larger than 1 and the n is an integer larger thanthe m.
 23. A semiconductor memory apparatus comprising: a duty cyclecorrection circuit configured to perform a duty correction operationwith respect to an input clock signal in response to a precharge signalto generate a corrected clock signal.
 24. The semiconductor memoryapparatus according to claim 23, wherein the duty cycle correctioncircuit comprises: a correction block configured to perform the dutycorrection operation with respect to the input clock signal in responseto an activation signal and generate the corrected clock signal; and anactivation signal generation block configured to generate the activationsignal in response to the precharge signal.
 25. The semiconductor memoryapparatus according to claim 24, wherein the correction block comprises:a correction execution unit configured to perform the duty correctionoperation with respect to the input clock signal based on a correctioncode and generate the corrected clock signal; a duty detection unitconfigured to generate a detection voltage based on a duty of the clocksignal; and a correction code generation unit configured to generate thecorrection code based on the detection voltage in response to theactivation signal.
 26. The semiconductor memory apparatus according toclaim 24, wherein the activation signal generation block is configuredto generate the activation signal with a predetermined pulse width whenthe precharge signal is activated.
 27. The semiconductor memoryapparatus according to claim 26, wherein the activation signalgeneration block is configured to allow the activation signal to have apredetermined pulse width using a pulse width of the clock signal.